Semiconductor memories, primarily DRAMs, are usually realized as a storage cell array on a semiconductor wafer. The storage cells comprises a storage capacitor and a selection transistor. In a read or write operation, respectively, the storage capacitor is charged or discharged, respectively, with an electrical charge corresponding to one data unit (bit) through the selection transistor. For this, the selection transistor is addressed through a bit- or wordline, respectively, by the aid of a peripheral logic having switching transistors.
A substantial center in the technological development of the semiconductor memories is the storage capacitor. In order to provide for sufficient storage capacity with small cross-sectional area, the storage capacitors are therefore realized in three-dimensional manner. As essential embodiments of three-dimensional storage capacitors, trench capacitors and stacked capacitors have gained acceptance. In trench capacitors, a trench is etched into the semiconductor substrate, which is filled with a dielectric interlayer and a first storage electrode layer, wherein a doped region of the semiconductor substrate around the trench serves as a second storage electrode layer. The selection transistor of the storage cell is usually formed on the semiconductor surface besides the trench capacitor as a planar field effect transistor, wherein the one transistor electrode is connected to the one electrode layer of the trench capacitor.
In contrast, stacked capacitors are formed on the surface of the semiconductor substrate, wherein a first storage electrode layer is realized in form of a crown, which is separated from a second storage electrode layer via a dielectric interlayer. The selection transistor of the storage cell is disposed in form of a planar field effect transistor below the stacked capacitor, wherein the one transistor electrode is connected to the crown-shaped storage electrode layer of the stacked capacitor.
Due to the continuously increasing downsizing of the semiconductor storage cells, also in three-dimensional storage capacitors, it is searched for additional possibilities to lower the area requirement and to increase the capacitor capacity at the same time.
Conventionally, in storage capacitors, material combinations of silica and/or silicon nitride are employed as the dielectric interlayer. However, for sub 100 nm structures, it is contemplated to replace the conventionally employed silica and/or silicon nitride layers by materials exhibiting a higher dielectric constant and thus allow increase of the storage capacity per unit area. As such so-called high k dielectrics, especially binary oxides such as alumina, tantalum oxide, hafnium oxide, zirconium oxide, oxides of the lanthanum group, alumina compounds and further single and mixed oxides are contemplated.
However, many of the contemplated high k dielectrics can only very difficultly be integrated into the standard process for producing storage capacitors within the bounds of the silicon planar technique, and especially only difficultly be formed as extremely thin layers. Further, the dielectric strength of many contemplated high k dielectrics is insufficient for employment in DRAM storage capacitors, especially concerning the long term stability. Furthermore, is has turned out that in many of the considered high k dielectrics, increased leakage currents occur with respect to the conventional material combinations of silica and/or silicon nitride, which entail shortened retaining time of the charge in the storage capacitor.
In employment of high k dielectrics within the bounds of the silicon planar technique, further, it has turned out that such layers result in high tensile stresses on the semiconductor surface, which in turn entails bending the semiconductor wafer. In employment of three-dimensional storage capacitors within the bounds of the DRAM production, due to the increased surface, therein, bends of several 100 μm can occur, whereby further processing the semiconductor substrate for device formation within the bounds of the silicon planar technique, wherein layers have to be applied consecutively precise in position, becomes nearly impossible. There is also the danger that the semiconductor wafer breaks due to the high stress.
These disadvantages especially apply to the employment of alumina (Al2O3) as a high k dielectric in storage capacitors, the preferred candidate for replacement of the conventional material combinations of silica and/or silicon nitride. Alumina distinguishes itself by being able to be relatively simply integrated into the standard process for producing storage capacitors within the bounds of the silicon planar technique. In producing storage capacitors with alumina as the dielectric interlayer within the bounds of the silicon planar technique, on a first capacitor electrode, which usually is a highly doped silicon layer, the alumina is deposited, which is subsequently thermally concentrated with a high-temperature process for improving the dielectric strength, for reducing the leakage current and for increasing the dielectric constant. Then, a second capacitor electrode layer, preferably a metal layer, is applied onto the alumina layer. In order to achieve sufficient dielectric strength with not too high leakage current at the same time, the concentrated alumina layer has to have a thickness of at least 5 nm, which results in high tensile stress on the substrate surface, which causes overlay problems in the subsequent processing.
With the employment of alumina, the dielectric constant of which is at 10, an increase of the storage capacity per unit area can be achieved over the conventionally employed dielectric interlayers of a material combination of silica and/or silicon nitride. However, compared to alumina, high k dielectrics with even substantially higher dielectric constant would be desirable for replacement of the conventionally employed silica and/or silicon nitride layers.
Thus, e.g. titanium oxide (TiO) exhibits a dielectric constant of greater than 40. However, titanium oxide has only a low thermal stability. Further, in titanium oxide layers, high leakage currents occur, and the dielectric strength over the lifetime of the storage capacitor is insufficient. These disadvantages basically also result from most of the other contemplated binary metal oxides, such as tantalum oxide having a dielectric constant of 25, or hafnium oxide having a dielectric constant of 25 to 30.
In order to achieve dielectric interlayers of a high k dielectric with improved electrical and mechanical characteristics, therefore, increasingly, also mixed layers are employed.
Preferably, they are produced in form of stacked layers with the aid of the atomic layer deposition (ALD) method, in which the mixed layer materials are applied separately from each other and mixed with a subsequent high-temperature process. Such an approach is described in US 2005/0233598 A1, among other things. Here, as the layer sequence, preferably, a metal oxide layer and silicon oxide or silicon oxy nitride are employed, respectively. However, the mixed layers proposed in US 2005/233598 A1 can only difficultly be integrated into the standard silicon planar technique methods. Further, the mixed layers also exhibit high leakage currents and an insufficient dielectric strength. However, primarily, the mixed layers result in high tensile stresses on the semiconductor surface and thus in strongly bending the semiconductor wafer.
There is a need for a method for producing a dielectric interlayer and for a storage capacitor with such a dielectric interlayer, which exhibit improved electrical and mechanical characteristics of the dielectric interlayer.